The FPGA level of design includes the development and implementation of FPGAs and PLDs. Ensuring a high-quality finished product at this level is crucial, since these chips act as the heart of the system. Some of the challenges that we often see include multi-FPGA designs, stubborn clock-reset-constraints (CRC) issues, greater complexity of the newer FPGA’s and stringent power requirements.
ProDigiSys works closely with clients to produce optimal designs that are cost-effective and reliable. We bring years of experience to the table and take pride in getting the design right the first time, saving downstream revisions and project delays.
Our specialized design services include the following areas:
RTL Design and Integration
We accomplish this part of the project in one of two ways:
- Working with you to develop design specifications for your chip and then leading subsequent validation and verification tests
- Using pre-existing design specifications and analyzing the functionality of your chip
Design and integration during this phase requires a thorough understanding of datapath implementation and optimization techniques including register balancing, multi-cycle paths and an understanding of how the FPGA will fit into the board design and overall system configuration.
Algorithm and IP Integration
Algorithm implementation ranges from a simple data-flow modeling approach to Xilinx SysGen / Mathwork’s Matlab modeling to using Xilinx’s High Level Synthesis (HLS) C based IP development tools. PDS can support your team with algorithm and IP integration. We can implement the “boring blocks” so your star engineer focuses on your next-generation IP. Our team follows the Xilinx Alliance eco-system strategy by supporting the pinnacle of the system, board, FPGA, domain, pyramid, you and your unique technology. Together your team’s vision becomes your reality.
The clocking resources available in most recent FPGA’s are significantly more complex, and require careful planning. PDS has successfully analyzed numerous clock trees, from simple to the most complex, and identified and solved issues of how they relate to the fabric and why. Our deep experience benefits your projects in speed and time-to-market.
At PDS we have the experience to configure soft core including Altera NIOS, Xilinx MicroBlaze, or embedded ARM core technology found in Xilinx’s Zync family.
Altera & Xilinx FPGA Design Experience
- Spartan 3/6
- Virtex II Pro /4 / 5 / 6
- Virtex 6 LXT & SXT
- 7 Series - Virtex, Artix, KintexZync
- Altera Cyclone III, Stratix IV
DSP Algorithm Implementation Experience
- Matlab / Simulink & Xilinx SysGen / HLS
Embedded System Implementation Experience
- PicoBlaze, MicroBlaze
- NIOS II
Our Clients Say It Best…
Success! I added your changes to my working model to check and confirm each one. Only a couple of very small adjustments were needed to the simulation. The simulation even runs at the crazy 39.543 us time step they requested. Mark Saddlemire, R&D Engineer, TCR Static VAR Compensation (SVR) Implementation, ALSTOM GRID
ProDigiSys successfully completed the FPGA development for the GPS III program. PDS did an outstanding job: first by adapting their design to accommodate peculiarities in our Space Ground Link Subsystem (SGLS) interfaces and later by adding signal polarity controls to provide us adaptability without additional FPGA programming. It’s been a pleasure to work with ProDigiSys. David Flanagan, Alf Systems Engineering, Lockheed Martin Space Systems – GPS III program
Phil, the ProDigiSys consultant, worked seamlessly with our team. His design experience and expertise enabled DSPCon to deliver an advanced software-defined radio to our military client that exceeded expectations. In working with Phil, our team experienced several unexpected design firsts: the multi-gigabit backplane links worked the first time; the SFP optical links worked the first time; and the embedded system design worked the first time. We admire PDS’ passion for digital systems and their dedication to first-time success. We look forward to working with them on our next digital system design project. Bob Franz, Chief Engineer and Subject Matter Expert – Hardware, DSPCon, Inc.
My group has drawn on ProDigiSys’ vast skills in the area of digital design for almost 10 years. PDS’ dedication to thorough and robust design practices is the reason we continually call on them for key digital design roles. ProDigiSys has the fortitude and persistence to draw on all available resources and tools to ensure designs will work the first time. Michael R. Piacentino, Technical Director – Vision Technologies, SRI
PDS enabled our ASIC team to implement a VHDL model in a Xilinx FPGA for testing in our lab. This accelerated our testing schedule, and they found bugs that we missed in behavioral simulations. Mike Low, Senior Engineer, TLSI
This algorithm project went above and beyond my expectations. A huge learning tool for us that is already paying dividends for issues we are having with our current projects. The same design “flaws” are showing up in Matlab simulations as they were in our lab simulations! Thanks a LOT for your help. Mark Saddlemire, R&D Engineer, TCR Static VAR Compensation (SVR) Implementation, ALSTOM GRID
ProDigiSys did another outstanding job for a space craft simulator project by reverse engineering PIC micro-controller display code for the 70V Power Relay Fuse Assembly. They recovered and documented the original code and found and fixed several intermittent design and implementation problems. Again their work was thorough, technically excellent, cost effective and, importantly, on schedule. Their work made our ultimate delivery to our customer a success. I recommend them highly for future hardware–software interface projects. David Flanagan, Alf Systems Engineering, Lockheed Martin Space Systems – GPS III program
PDS was attentive to our needs and even when offsite, their engineer remotely logged onto our system and helped us debug some Verilog code. Senior RF/Hardware Engineer, MOOG