One of our customers whom we had previously supported with the debug of poor signal-to-noise ratio performance on their 12-bit ADC cards approached ProDigiSys for support with a new software defined radio (SDR) set. No off-the-shelf system cards could be used as size, weight and power (SWaP) needed to be reduced to the lowest levels.
The system in question would have eight input ADC cards to capture I & Q baseband signals. The ADC cards would be built from scratch, as Analog Devices’ new gigahertz speed ADCs were just coming off the line, so no standard 3U or 6U Eurocard form factor product existed in the market.
Furthermore, our customer decided to define a form factor, BFX. 3U and 6U VME/VPX card sizes were deemed too large, so we set about designing a square 4″ x 4″ card that would leverage the newest PCIe gen 2 technology for communicating the vast amount of ADC data at 5 Gb/s to data consumption cards. At the time, these data consumption cards used the Virtex-5 SX 95T. If successful, Virtex-5 SX240 T devices would be used later since these two members of the Xilinx Vitex-5 SX family shared a similar package/footprint, if new data algorithms were made available. The custom backplane ended up with 21 slots.
PDS’ dedication, attention to detail, prior Xilinx experience and cross-disciplinary management skills contributed to success in creating the new 21 slot multi-channel SDR system in 9-months.
In addition to ADC channel cards and data engine cards, a PCIe switch card (using the largest PLX switch available at the time) system clock card with a custom PLL frequency was used. The data engine cards supported dual fiber-optic SFP ports. PDS was charged with the system design, passive backplane and the design of each unique card. We designed the schematics and the PCB packing including the layer stack up and engineering specifications for critical nets including ADC sample clock jitter. We also wrote the HDL demonstration code for all major interfaces, including source synchronous interfaces for the high-speed ADC channels.
Many first-time successes were experienced with this major design project. PCIe channels worked as designed, fiber-optic channels worked as designed, ADC interfacing worked as designed and system clocking performance met stringent system specifications. The completed system was delivered for algorithm implementation.
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